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? semiconductor components industries, llc, 2015 june, 2015 ? rev. 7 1 publication order number: NCP5104/d NCP5104, ncv5104 high voltage, half bridge driver the NCP5104 is a high voltage power gate driver providing two outputs for direct drive of 2 n?channel power mosfets or igbts arranged in a half?bridge configuration. it uses the bootstrap technique to insure a proper drive of the high?side power switch. features ? high voltage range: up to 600 v ? dv/dt immunity 50 v/nsec ? gate drive supply range from 10 v to 20 v ? high and low drive outputs ? output source / sink current capability 250 ma / 500 ma ? 3.3 v and 5 v input logic compatible ? up to v cc swing on input pins ? extended allowable negative bridge pin voltage swing to ?10 v for signal propagation ? matched propagation delays between both channels ? 1 input with internal fixed dead time (520 ns) ? under v cc lockout (uvlo) for both channels ? pin to pin compatible with industry standards ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? half?bridge power converters soic?8 d suffix case 751 marking diagrams NCP5104 = specific device code a = assembly location l or wl = wafer lot y or yy = year w or ww = work week g or = pb?free package www. onsemi.com 1 pdip?8 p suffix case 626 p5104 alyw 1 8 1 NCP5104 awl yywwg pinout information 8 pin package 2 3 4 1 7 6 5 8 sd in vcc gnd vboot drv_hi bridge drv_lo device package shipping ? ordering information NCP5104pg pdip?8 (pb?free) 50 units / rail ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. NCP5104dr2g soic?8 (pb?free) 2500 / tape & ree l ncv5104dr2g soic?8 (pb?free) 2500 / tape & ree l
NCP5104, ncv5104 www. onsemi.com 2 vcc in gnd drv_lo bridge drv_hi vboot q1 q2 c6 c4 c3 gnd gnd gnd ncp1395 vcc gnd vbulk c1 gnd out+ out? u2 r1 d3 gnd l1 c3 d2 t1 d4 lf vcc 3 in 2 1 gnd 4 drv_lo 5 bridge 6 drv_hi 7 vboot 8 u1 NCP5104 figure 1. typical application resonant converter (llc type) figure 2. typical application half bridge converter d1 + + q1 q2 c6 c4 c3 gnd gnd gnd vcc gnd vbulk c1 gnd out+ out? u2 r1 d3 gnd l1 c3 d2 t1 d4 3 2 1 4 5 6 7 8 u1 NCP5104 d1 + + c5 sg3526 mc34025 tl594 ncp1561 sd sd r s q pulse trigger gnd gnd gnd vcc in vboot drv_hi bridge drv_lo gnd vcc vcc uv detect delay gnd uv detect level shifter q figure 3. detailed block diagram sd dead time generation
NCP5104, ncv5104 www. onsemi.com 3 pin description pin name description v cc maximum ratings rating symbol value unit v cc main power supply voltage ?0.3 to 20 v v cc_transient main transient power supply voltage: iv cc_max = 5 ma during 10 ms 23 v v boot vhv: high voltage boot pin ?1 to 620 v v bridge vhv: high voltage bridge pin ?1 to 600 v v bridge allowable negative bridge pin voltage for in_lo signal propagation to dr v_lo (see characterization curves for detailed results) ?10 v v boot? v bridge vhv: floating supply voltage ?0.3 to 20 v v drv_hi vhv: high side output voltage v bridge ? 0.3 to v boot + 0.3 v v drv_lo low side output voltage ?0.3 to v cc + 0.3 v dv bridge /dt allowable output slew rate 50 v/ns v in , v sd inputs in & sd ?1.0 to v cc + 0.3 v esd capability: ? hbm model (all pins except pins 6?7?8 in 8) ? machine model (all pins except pins 6?7?8) 2 200 kv v latch up capability per jedec jesd78 r ja power dissipation and thermal characteristics pdip?8: thermal resistance, junction?to?air so?8: thermal resistance, junction?to?air 100 178 c/w t st storage temperature range ?55 to +150 c t j_max maximum operating junction t emperature +150 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be af fected.
NCP5104, ncv5104 www. onsemi.com 4 electrical characteristic (v cc = v boot = 15 v, v gnd = v bridge , ?40 c < t j < 125 c, outputs loaded with 1 nf) rating symbol t j ?40 c to 125 c units min typ max output section output high short circuit pulsed current v drv = 0 v, pw 10 s (note 1) i drvsource ? 250 ? ma output low short circuit pulsed current v drv = vcc, pw 10 s (note 1) i drvsink ? 500 ? ma output resistor (typical value @ 25 c) source r oh ? 30 60 output resistor (typical value @ 25 c) sink r ol ? 10 20 high level output voltage, v bias ?v drv_xx @ i drv_xx = 20 ma v drv_h ? 0.7 1.6 v low level output voltage v drv_xx @ i drv_xx = 20 ma v drv_l ? 0.2 0.6 v dynamic output section turn?on propagation delay (vbridge = 0 v) (note 2) t on ? 620 800 ns turn?off propagation delay (vbridge = 0 v or 50 v) (note 3) t off ? 100 170 ns shutdown propagation delay, when shutdown is enabled t sd_en ? 100 170 ns shutdown propagation delay, when shutdown is disabled t sd_dis ? 620 800 ns output voltage rise time (from 10% to 90% @ v cc = 15 v) with 1 nf load t r ? 85 160 ns output voltage fall time (from 90% to 10% @ v cc = 15 v) with 1 nf load t f ? 35 75 ns propagation delay matching between the high side and the low side @ 25 c (note 4) t ? 10 45 ns internal fixed dead time (note 5) dt 400 520 650 ns input section low level input voltage threshold v in ? ? 0.8 v input pull?down resistor (v in < 0.5 v) r in ? 200 ? k high level input voltage threshold v in 2.3 ? ? v logic ?1? input bias current @ v in = 5 v @ 25 c i in+ ? 5 25 a logic ?0? input bias current @ v in = 0 v @ 25 c i in? ? ? 2.0 a supply section vcc uv start?up voltage threshold vcc_stup 8.0 8.9 9.8 v vcc uv shut?down voltage threshold vcc_shtdwn 7.3 8.2 9.0 v hysteresis on vcc vcc_hyst 0.3 0.7 ? v vboot start?up voltage threshold reference to bridge pin (vboot_stup = vboot ? vbridge) vboot_stup 8.0 8.9 9.8 v vboot uv shut?down voltage threshold vboot_shtdwn 7.3 8.2 9.0 v hysteresis on vboot vboot_shtdwn 0.3 0.7 ? v leakage current on high voltage pins to gnd (v boot = v bridge = drv_hi = 600 v) i hv_leak ? 5 40 a consumption in active mode (vcc = vboot, fsw = 100 khz and 1 nf load on both driver outputs) icc1 ? 4 5 ma consumption in inhibition mode (vcc = vboot) icc2 ? 250 400 a vcc current consumption in inhibition mode icc3 ? 200 ? a vboot current consumption in inhibition mode icc4 ? 50 ? a product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. parameter guaranteed by design. 2. t on = t off + dt 3. turn?off propagation delay @ vbridge = 600 v is guaranteed by design. 4. see characterization curve for t parameters variation on the full range temperature. 5. timing diagram definition see: figure 4, figure 5 and figure 6.
NCP5104, ncv5104 www. onsemi.com 5 figure 4. input/output timing diagram in drv_hi drv_lo sd note: dr v_hi output is in phase with the input figure 5. timing definitions 50% 90% 10% ton toff 50% 90% toff 10% drv_hi drv_lo in dead time dead time 90% tr tr 90% 10% tf 10% tf ton ton = toff + dt
NCP5104, ncv5104 www. onsemi.com 6 figure 6. matching propagation delay definition 90% 50% deadtime1 toff_hi 10% drv_hi in 50% 10% toff_lo deadtime2 90% drv_lo matching delay1=toff_hi?tof f_lo matching delay 2=(toff_lo+dt1)?(tof f_hi+dt2) figure 7. shutdown waveform definition 10% 50% tsd_dis 90% 50% tsd_en drv_hi drv_lo sd
NCP5104, ncv5104 www. onsemi.com 7 characterization curves 400 450 500 550 650 700 750 800 10 12 14 16 18 20 v cc , voltage (v) t on , propagation delay (ns) figure 8. turn on propagation delay vs. supply voltage (v cc = v boot ) t on high side t on low side 400 450 550 600 700 750 850 900 ?40 ?20 0 20 40 60 80 100 120 temperature ( c) t on , propagation delay (ns) figure 9. turn on propagation delay vs. temperature t on low side t on high side 0 20 40 60 80 100 140 160 10 12 14 16 18 20 v cc , voltage (v) t off , propagation delay (ns) figure 10. turn off propagation delay vs. supply voltage (v cc = v boot ) t off high side t off low side 0 20 40 60 80 100 120 160 ?40 ?20 0 20 40 60 80 100 120 temperature ( c) t off , propagation delay (ns) figure 11. turn off propagation delay vs. temperature 0 100 200 300 400 500 600 800 01020304050 v bridge voltage (v) t on , propagation delay (ns) figure 12. high side turn on propagation delay vs. v bridge voltage (v cc = v boot ) 0 20 40 60 80 100 120 140 160 0 1020304050 v bridge voltage (v) t off , propagation delay (ns) figure 13. high side turn off propagation delay vs. v bridge voltage (v cc = v boot ) t off high side t off low side 600 500 650 800 140 120 700
NCP5104, ncv5104 www. onsemi.com 8 characterization curves 0 20 40 60 80 100 120 140 160 10 12 14 16 18 20 v cc , voltage (v) t on , risetime (ns) figure 14. turn on risetime vs. supply voltage (v cc = v boot ) t r high side t r low side 0 20 40 60 80 100 120 160 ?40 ?20 0 20 40 60 80 100 12 0 t r low side t r high side temperature ( c) t on , risetime (ns) figure 15. turn on risetime vs. temperature 0 10 20 30 40 50 60 70 80 10 12 14 16 18 20 t off , falltime (ns) v cc , voltage (v) figure 16. turn off falltime vs. supply voltage (v cc = v boot ) t f low side t f high side 0 10 20 30 40 50 ?40 ?20 0 20 40 60 80 100 12 0 t f low side t f high side t off , falltime (ns) temperature ( c) figure 17. turn off falltime vs. temperature ?20 ?15 ?10 5 20 ?40 ?20 0 20 40 60 80 100 120 propagation delay matching (ns) temperature ( c) figure 18. propagation delay matching between high side and low side driver vs. temperature 60 140 ?5 0 10 15 delay matching 1 delay matching 2 400 450 600 ?40 ?20 0 20 40 60 80 100 12 0 dead time (ns) temperature ( c) figure 19. dead t ime vs. temperature 500 550
NCP5104, ncv5104 www. onsemi.com 9 characterization curves 0 0.2 0.4 0.6 0.8 1.0 1.2 1.6 ?40 ?20 0 20 40 60 80 100 120 low level input voltage threshold (v) temperature ( c) figure 20. low level input voltage threshold vs. supply voltage (v cc = v boot ) 0 0.5 1.0 1.5 2.0 2.5 10 12 14 16 18 20 high level input voltage threshold (v) v cc , voltage (v) figure 21. low level input voltage threshold vs. temperature 0 0.5 1.0 1.5 2.0 2.5 ?40 ?20 0 20 40 60 80 100 120 high level input voltage threshold (v) temperature ( c) figure 22. high level input voltage threshold vs. supply voltage (v cc = v boot ) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 10 12 14 16 18 20 logic ?0? input current ( a) v cc , voltage (v) figure 23. high level input voltage threshold vs. temperature 0 2.0 4.0 6.0 8.0 10 ?40 ?20 0 20 40 60 80 100 120 logic ?0? input current ( a) temperature ( c) figure 24. logic ?0? input current vs. supply voltage (v cc = v boot ) figure 25. logic ?0? input current vs. temperature 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 10 12 14 16 18 20 low level input voltage threshold (v) v cc , voltage (v) 1.4
NCP5104, ncv5104 www. onsemi.com 10 characterization curves 0 2.0 4.0 6.0 8.0 10 ?40 ?20 0 20 40 60 80 100 120 logic ?1? input current ( a) temperature ( c) figure 26. logic ?1? input current vs. supply voltage (v cc = v boot ) 0 0.2 0.4 0.6 0.8 1.0 10 12 14 16 18 20 low level output voltage threshold (v) v cc , voltage (v) figure 27. logic ?1? input current vs. temperature 0 0.2 0.4 0.6 0.8 1.0 ?40 ?20 0 20 40 60 80 100 120 low level output voltage (v) temperature ( c) figure 28. low level output voltage vs. supply voltage (v cc = v boot ) 0 0.4 0.8 1.2 1.6 10 12 14 16 18 20 high level output voltage threshold (v) v cc , voltage (v) figure 29. low level output voltage vs. temperature 0 0.4 0.6 0.8 1.0 ?40 ?20 0 20 40 60 80 100 120 high level output voltage (v) temperature ( c) figure 30. high level output voltage vs. supply voltage (v cc = v boot ) figure 31. high level output voltage vs. temperature 0 1 2 3 4 5 6 7 8 10 12 14 16 18 20 logic ?1? input current ( a) v cc , voltage (v) 0.2
NCP5104, ncv5104 www. onsemi.com 11 characterization curves output source current (ma) temperature ( c) figure 32. output source current vs. supply voltage (v cc = v boot ) 0 50 100 150 200 250 300 350 400 ?40 ?20 0 20 40 60 80 100 120 i src high side i src low side 0 100 200 300 400 500 600 10 12 14 16 18 20 i sink high side i sink low side output sink current (ma) v cc , voltage (v) figure 33. output source current vs. temperature 0 100 200 300 400 500 600 ?40 ?20 0 20 40 60 80 100 120 output sink current (ma) temperature ( c) figure 34. output sink current vs. supply voltage (v cc = v boot ) i sink low side i sink high side 0 0.04 0.08 0.12 0.16 0.20 0 100 200 300 400 500 600 high side leakage current on hv pins to gnd ( a) hv pins voltage (v) figure 35. output sink current vs. temperature 0 5.0 10 15 20 ?40 ?20 0 20 40 60 80 100 120 leakage current on high voltage pins (600 v) to gnd ( a) temperature ( c) figure 36. leakage current on high voltage pins (600 v) to ground vs. v bridge voltage (v bridge = v boot = v drv_hi ) figure 37. leakage current on high voltage pins (600 v) to ground vs. temperature (v bridge = v boot = v drv_hi = 600 v) 0 50 100 150 200 250 300 350 400 10 12 14 16 18 20 i src high side i src low side output source current (ma) v cc , voltage (v) 0.02 0.06 0.10 0.14 0.18
NCP5104, ncv5104 www. onsemi.com 12 characterization curves 0 20 40 60 80 100 ?40 ?20 0 20 40 60 80 100 120 v boot current supply ( a) temperature ( c) figure 38. v boot supply current vs. bootstrap supply voltage (v cc = v boot ) 0 40 80 120 160 200 240 0 4.0 8.0 12 16 20 v cc supply current ( a) v cc , voltage (v) figure 39. v boot supply current vs. temperature 0 100 200 300 400 ?40 ?20 0 20 40 60 80 100 120 v cc current supply a) temperature ( c) figure 40. v cc supply current vs. v cc supply voltage (v cc = v boot ) 8.0 8.2 8.4 8.6 8.8 9.0 9.2 9.4 9.6 9.8 10 ?40 ?20 0 20 40 60 80 100 120 v cc uvlo startup v boot uvlo startup uvlo startup voltage (v) temperature ( c) figure 41. v cc supply current vs. temperature 7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6 8.8 9.0 ?40 ?20 0 20 40 60 80 100 120 uvlo shutdown voltage (v) temperature ( c) figure 42. uvlo startup voltage vs. temperature v cc uvlo shutdown v boot uvlo shutdown figure 43. uvlo shutdown voltage vs. temperature 0 20 40 60 80 100 0 4.0 8.0 12 16 20 v boot supply current ( a) v boot , voltage (v) 50 150 250 350
NCP5104, ncv5104 www. onsemi.com 13 characterization curves 0 5.0 10 15 20 25 30 40 0 100 200 300 400 500 600 r gate = 0 r c load = 2.2 nf/q = 33 nc i cc + i boot current supply (ma) switching frequency (khz) figure 44. i cc1 consumption vs. switching frequency with 15 nc load on each driver @ v cc = 15 v r gate = 10 r r gate = 22 r 0 10 20 30 40 50 60 0 100 200 300 400 500 600 r gate = 0 r r gate = 10 r r gate = 22 r i cc + i boot current supply (ma) switching frequency (khz) figure 45. i cc1 consumption vs. switching frequency with 33 nc load on each driver @ v cc = 15 v c load = 3.3 nf/q = 50 nc 0 10 30 40 60 70 80 0 100 200 300 400 500 600 i cc + i boot current supply (ma) switching frequency (khz) figure 46. i cc1 consumption vs. switching frequency with 50 nc load on each driver @ v cc = 15 v r gate = 0 r r gate = 10 r r gate = 22 r c load = 6.6 nf/q = 100 nc figure 47. i cc1 consumption vs. switching frequency with 100 nc load on each driver @ v cc = 15 v 0 5.0 10 15 20 25 0 100 200 300 400 500 600 r gate = 0 r to 22 r c load = 1 nf/q = 15 nc i cc + i boot current supply (ma) switching frequency (khz) 35 50 20 figure 48. NCP5104, negative voltage safe operating area on the bridge pin ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 100 200 300 400 500 600 ?40 c 25 c 125 c negative pulse voltage (v) negative pulse duration (ns)
NCP5104, ncv5104 www. onsemi.com 14 package dimensions 8 lead pdip case 626?05 issue n 14 5 8 b2 note 8 d b l a1 a eb e a top view c seating plane 0.010 ca side view end view end view with leads constrained dim min max inches a ???? 0.210 a1 0.015 ???? b 0.014 0.022 c 0.008 0.014 d 0.355 0.400 d1 0.005 ???? e 0.100 bsc e 0.300 0.325 m ???? 10 ??? 5.33 0.38 ??? 0.35 0.56 0.20 0.36 9.02 10.16 0.13 ??? 2.54 bsc 7.62 8.26 ??? 10 min max millimeters notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. dimensions a, a1 and l are measured with the pack- age seated in jedec seating plane gauge gs?3. 4. dimensions d, d1 and e1 do not include mold flash or protrusions. mold flash or protrusions are not to exceed 0.10 inch. 5. dimension e is measured at a point 0.015 below datum plane h with the leads constrained perpendicular to datum c. 6. dimension e3 is measured at the lead tips with the leads unconstrained. 7. datum plane h is coincident with the bottom of the leads, where the leads exit the body. 8. package contour is optional (rounded or square corners). e1 0.240 0.280 6.10 7.11 b2 eb ???? 0.430 ??? 10.92 0.060 typ 1.52 typ e1 m 8x c d1 b a2 0.115 0.195 2.92 4.95 l 0.115 0.150 2.92 3.81 h note 5 e e/2 a2 note 3 m b m note 6 m
NCP5104, ncv5104 www. onsemi.com 15 package dimensions soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent? marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or othe r applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death ma y occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidi aries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of per sonal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. sci llc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP5104/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your lo cal sales representative

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